(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to create a crown shaped, capacitor structure, for a dynamic random access memory, (DRAM), device.
(2) Description of Prior Art
The semiconductor industry is continually striving to increase device performance. The performance, or strength of signal, of a DRAM device, is strongly dependent on the capacitor structure, used for the DRAM device. The design often used for DRAM capacitors, is a stacked capacitor configuration, comprised with the stacked capacitor structure, overlying a transfer gate transistor, communicating with the underlying transfer gate transistor, via a connecting storage node structure. However the trend to micro-miniaturization, or the use of sub-micron features, have resulted in a reduction in the horizontal dimension, allotted for a specific transfer gate transistor, thus the dimension of an overlying stacked capacitor structure, is now limited. Therefore capacitance increases, needed for enhanced performance, can not be achieved via increasing the horizontal dimension of the stacked capacitor structure.
The solution for increasing DRAM capacitance, while still deceasing the horizontal dimension of the transfer gate transistor, or of the DRAM cell, has been successfully addressed, via use of either a crown shaped, capacitor structure, and/or the use of a hemispherical grain, (HSG), silicon layer, used as the top surface of the storage node component of the capacitor structure. The crown shaped, capacitor structure, featuring a crown shaped storage node structure, comprised of vertical, as well as horizontal features, increases. the surface area of the storage node structure as a result of the vertical features. Yang et al, in U.S. Pat. No. 5,677,227, describe crown shaped capacitor structures, comprised with numerous polysilicon features, offering increased storage node surface area, and thus increased capacitance when compared to counterparts fabricated using flat storage node shapes. The use of an HSG silicon layer, on the top surface of a storage node structure, increases surface area via the convex and concave features of the HSG silicon layer. Tsai, in U.S. Pat. No. 5,763,306, describes a method for fabricating a capacitor structure, featuring an HSG silicon layer, on the top surface of a storage node shape. In addition, capacitor structures have been fabricating using the combination of an HSG silicon layer, on the top surface of a crown shaped, storage node structure, offering increased surface area via use of both approaches.
The fabrication of a crown shaped storage node structure, is accomplished via formation of a capacitor opening, in an insulator layer; depositing an HSG silicon/ polysilicon layer; followed by the removal of the regions of the HSG silicon/polysilicon layer, residing on the top surface of the insulator layer, resulting in the desired crown shaped, storage node shape, in the capacitor opening, comprised of vertical HSG silicon/polysilicon features, on the sides of the capacitor opening, and a horizontal, HSG silicon/polysilicon feature, at the bottom of the capacitor opening, connecting the vertical HSG silicon/polysilicon features. The removal of the HSG silicon/polysilicon regions, from the top surface of the insulator layer is accomplished via a chemical mechanical polishing, (CMP), procedure, used to remove the desired regions of HSG silicon/polysilicon, without disturbing the HSG silicon/polysilicon horizontal feature, located at the bottom of the capacitor opening. However the CMP, used is this situation, can place unwanted particles, either from the CMP slurry, of from the removed HSG/polysilicon layer, at the bottom of the capacitor opening, overlying the horizontal HSG silicon/polysilicon, component, and interfering with the subsequent formation of an overlying capacitor dielectric layer. The use of a photoresist plug, located in the capacitor opening, only exposing the regions of HSG silicon/polysilicon, located on the top surface of the insulator layer, results in the same particles, now formed on the top surface of the photoresist plug, instead of being located at the bottom of the capacitor opening. However selective removal of the photoresist plug, via plasma oxygen ashing, results in the non-volatilized particles, falling into the bottom of the capacitor opening, again adversely influencing the subsequent formation of the capacitor dielectric layer.
This invention will offer a procedure for fabricating HSG silicon/polysilicon, crown shaped storage node structures, in which the particles presented by the needed CMP procedure, is successfully addressed. A first wet procedure, using a solution of NH.sub.4 OH and H.sub.2 O.sub.2, is used to remove the unwanted particles, from the top surface of a photoresist plug, after the CMP procedure, and prior to removal of the photoresist plug. Next a H.sub.2 SO.sub.4 and H.sub.2 O.sub.2 solution is employed to clean the HSG silicon surface, prior to the formation of an overlying capacitor dielectric layer. These novel wet clean procedures, at these specific process stages. have not been offered in any of the prior art addressing crown shaped, as well as HSG silicon, capacitor structures.